TECHNOLOGY/BUSINESS OPPORTUNITY Low-Cost Laminated Chip Slapper

Opportunity: Lawrence Livermore National Laboratory (LLNL), operated by the Lawrence Livermore National Security (LLNS), LLC under contract no. DE-AC52-07NA27344 (Contract 44) with the U.S. Department of Energy (DOE), is offering the opportunity to partner to further develop and license for commercialization its novel low-cost laminated chip slapper technology.Background: A slapper detonator also known as an exploding foil initiator (EFI) was originally developed by LLNL under US Patent US4788913 A. It was invented as an advancement to exploding bridgewire (EBW) detonators. Initiating secondary explosives in a safe and reliable manner is a technical problem. The benefit of an EFI detonator is that it is not in direct contact with the explosive element and the flyer layer protects the conductive bridge from the environment. These aspects increases both the safety and reliability of the detonator. The current manufacturing method first deposits a conductive metal layer and then etches

the metal layer to form a narrow bridge. The flyer layer is also deposited on, usually through spin coating of polyimide. These are both expensive processes. The main benefit of the new process is the cost efficiency. Instead of etching, a kapton mask is used to define the shape of the bridge. This mask process allows for the ability to easily customize the shape and size of the conductive bridge portion of the chip slapper.Description:  Livermore researchers have developed a chip slapper consisting of a substrate with a conductive bridge layer and a flyer layer on one side of the substrate. The other side of the substrate consists of conductive pads. The bridge side of the substrate is electrically connected to the pad side of the substrate through a conductive pathway. The design and shape of the conductive bridge is manufactured using a masked physical vapor deposition process. The flyer layer is applied using a lamination technique.There are four key elements of the invention:First, is the production of the substrate. The substrate is a custom made alumina ceramic wafer. The bottom side of the wafer has a pattern of electroplated gold pads. A pattern of via holes are laser drilled and plated with gold to create a conductive pathway between the surfaces of the substrate.The second element of the invention is the metalization of the conductive bridge to the top side of the substrate. A shadow mask is laser cut out of Kapton which establishes the pattern and shape of the conductive bridge. A machined "strongback" is cut to a similar but over sized pattern. The strongback is used to hold the Kapton mask flat during the vapor deposition process. The assembly is then run through an E-beam vapor deposition process to deposit the conductive bridge onto the surface of the substrate.The third element is the application of the "slapper" layer. A layer of kapton is adhered over the conductive bridge surface of the substrate using Pyralux adhesive. The lamination process is performed under vacuum.Fourth, the wafer is diced into individual chip slappers.  The novel aspects of the invention include the masked/PVD process of defining the bridge profile, use of electroplated substrate with plated vias, and the laminated slapper.Advantages:  The advantages of LLNL’s low-cost laminated chip slapper include the masked/PVD process of defining the bridge profile, use of electroplated substrate with plated vias, and the laminated slapper.-        Greatly simplifies fabrication (reduce fab cost by 5-10X os some key steps)-        Useful for applications requiring high voltage standoff-        Masked vapor deposition process allows for easily customizable wafer and bridge design-        Uniform flyer thickness and virtually defect freePotential Applications:  Uses of this technology include shock initiation of explosives, military ordnance, mining and explosive welding.Development Status:  Preliminary tests have yielded increased performance in the chip slapper. The new process is delivering better performance at a lower cost.LLNL has filed a U.S. Patent Application for this technology IL-13267 Low Cost Chip Slapper (U.S. Patent Application 15/982580)See attached file for summary quad chart.LLNL is seeking industry partners with a demonstrated ability to bring such inventions to the market. Moving critical technology beyond the Laboratory to the commercial world helps our licensees gain a competitive edge in the marketplace. All licensing activities are conducted under policies relating to the strict nondisclosure of company proprietary information.  Please visit the IPO website at https://ipo.llnl.gov/resources for more information on working with LLNL and the industrial partnering and technology transfer process.Note:  THIS IS NOT A PROCUREMENT:  Companies interested in commercializing LLNL's low-cost laminated chip slapper technology should provide a written statement of interest, which includes the following: 1.   Company Name and address.2.   The name, address, and telephone number of a point of contact.3.     A description of corporate expertise and facilities relevant to commercializing this technology. Written responses should be directed to:Lawrence Livermore National LaboratoryInnovation and Partnerships OfficeP.O. Box 808, L-795Livermore, CA  94551-0808Attention:  FBO 406-18 Please provide your written statement within thirty (30) days from the date this announcement is published to ensure consideration of your interest in LLNL's low-cost laminated chip slapper technology. Contact Information: Connie L Pitcock, Administration, Phone 925-422-1072, Fax 925-423-8988, Email pitcock1@llnl.gov Office Address :7000 East AvenueL-795 Livermore CA 94550 Location: Industrial Partnerships & Commercialization Set Aside: N/A